Field of the Invention
The present invention relates generally to a semiconductor device including a MOS (Metal Oxide Semiconductor) field effect transistor and a manufacturing method thereof, and more specifically, to a technique which allows preventing of punch through phenomenon and miniaturization of channel lengths.
Description of the Background Art
With high-density integration of semiconductor circuit devices in recent years, it has been an important object to achieve successfully the delicate adjustment of impurity concentration distribution in the depth direction of an impurity diffusion layer to be source/drain regions, in order to maintain the design characteristics of MOS field effect transistors.
Now, description will be provided on a process of forming an impurity diffusion layer to be the source/drain regions of a conventional MOS field effect transistor (e.g. see Japanese Patent Publication No. 62-7703) by way of illustration in conjunction with FIGS. 1A through 5B. FIGS. 1A through 5B show sequentially the process of forming an impurity diffusion layer to be source/drain regions and the resulting impurity concentration distributions in the depth direction, i.e., as a function of depth from the surface of the substrate, in an MOS field effect transistor having a conductive layer formed of polycrystalline silicon to be connected to the source/drain regions and using the conductive layer as an interconnection.
In the process of forming this conventional MOS field effect transistor, referring to FIG. 1A, after the surface and sidewalls of a gate electrode 3 formed on the surface of a p type semiconductor substrate 1 with a gate insulating film 2 therebetween are covered with an insulating film 4, an n type impurity is implanted into the surface of semiconductor substrate 1 under prescribed conditions. Impurity concentration distribution in its depth direction immediately after implanting arsenic, for example, as the n type impurity at an implantation energy of 60 KeV, in a dose of 1.times.10.sup.15 /cm.sup.2 is shown in a graphic representation in FIG. 1B.
An impurity diffusion layer 5 is thereafter formed by means of prescribed thermal treatment. (see FIG. 2A.) The concentration distribution of the impurity in its depth direction after the thermal diffusion varies rather gently as shown in FIG. 2B as compared to that immediately after the implantation.
Referring to FIG. 3, a polycrystalline silicon layer 6 is deposited as thick as approximately 1500 .ANG., and patterning is performed so as to cover at least the surface of impurity diffusion layer 5. Thereafter, an n type impurity is implanted so that the peak of the impurity concentration is in polycrystalline silicon layer 6. (see FIG. 4A.) The concentration distribution of the impurity in its depth direction in the above-described state is as shown in FIG. 4B, if arsenic, for example, is implanted at 60 KeV, in a dose of 1.times.10.sup.15 /cm.sup.2.
The impurity in polycrystalline silicon layer 6 is activated by means of another thermal treatment, rendering polycrystalline silicon layer 6 conductive. (see FIG. 5A.) The concentration distribution of the impurity in its depth direction in the above-described state is as shown in FIG. 5B.
In the case of a very small MOS field effect transistor having a channel length less than 1.0 .mu.m, especially less than 0.5 .mu.m, the depth of a region having a concentration more than the minimum concentration [B] (1.times.10.sup.19 /cm.sup.3 in FIG. 5B) which effects on electrical conduction is [C] (approximately 0.25 .mu.m in FIG. 5B) in order to keep the peak impurity concentration of impurity diffusion layer 5 at the level of concentration [A] (about 10.sup.20 /cm.sup.3 in FIG. 5B) necessary for keeping the resistance of impurity diffusion layer 5 low. When the depth [C] attains the level with little effect of the field created by gate electrode 3 formed on the surface of semiconductor substrate 1, voltage applied to the drain allows a depletion layer extend into semiconductor substrate 1 and further to reach the source, resulting in more frequent occurrence of a so-called punch through phenomenon. The state inside semiconductor substrate 1 at that time is shown by potential line distribution illustrating a cross section of a MOS field effect transistor with a channel length of 1 .mu.m in its channel lengthwise direction (see FIG. 6A) and by electron density distribution (see FIG. 6B). FIGS. 6A and 6B are published in Solid State Electronics Vol. 22,1979, P69. It can be understood from these figures that the equipotential lines of source/drain regions come close to each other at point S in FIG. 6A and the density of electrons is higher in a channel region at a position as deep as the source/drain region having an electron density of 10.sup.20 /cm.sup.3 than in the surface of semiconductor substrate 1. A graphic representation in FIG. 7 illustrates the relation between drain voltage V.sub.DS and drain current I.sub.D, using a gate voltage V.sub.GS as a parameter. As can be seen from FIG. 7, even if the gate voltage V.sub.GS is set to be 0 V, the drain current I.sub.D flowing between the source/drain regions can not be nullified, and, therefore, the drain current I.sub.D cannot be controlled by the value of V.sub.GS. Application of such a MOS field effect transistor, for example, to a DRAM (Dynamic Random Access memory) can give rise to troubles in the device, and it has been difficult to form a very small MOS field effect transistor having a channel length less than 1 .mu.n.
The factors responsible for the above-described problem as well as ideal concentration distribution in the direction of the depth of impurity diffusion layer 5 for solving this problem will be illustrated by a typical example of simplified model shown in FIGS. 8A to 8C.
Assume, for example, a MOS field effect transistor having a cross sectional structure of a simplified model as shown in FIGS. 8A and 8B. FIG. 8A sets forth a case in which the depth of a source/drain region (impurity diffusion layer 5) from the surface of semiconductor substrate 1 is relatively large, and FIG. 8B sets forth a case in which the depth is small as compared to the former FIG. 8A case. With the concentration density of the p type impurity of semiconductor substrate 1 being constant, when gate electrode 3 is grounded, the depth of semiconductor substrate 1 which is affected by the electric field is naturally decided. The part indicated by broken declined lines in FIGS. 8A and 8B shows a range which can be controlled by the electric field so as not to be inverted when gate electrode 3 is grounded.
As shown in FIG. 8B, if impurity diffusion layer 5 is within the range which can be controlled by gate electrode 3, there will be no punch through, but if, as shown in FIG. 8A, the bottom of impurity diffusion layer 5 is beyond the range of control by gate electrode 3, current flows through this deep part, resulting in punch through.
However, if impurity diffusion layer 5 is too shallow, the resistance of current flowing through the part becomes too high, and therefore, the adjustment of the depth of impurity diffusion layer 5 is one significant matter.